============================================================================= Anomie's SPC700 Cycle Doc $Revision: 1126 $ $Date: 2007-04-21 15:07:05 -0400 (Sat, 21 Apr 2007) $ ============================================================================= 1 Register, Immediate -- A,#i; X,#i; Y,#i (ADC,AND,CMP,CMP,CMP,EOR,MOV,MOV,MOV,OR,SBC) (2 bytes) (2 cycles) 1 PC Op Code 1 2 PC+1 Data 1 * This should be accurate. 2 Register, Register -- A,X; A,Y; X,A; X,Y; Y,A; Y,X; SP,X; X,SP (MOV,MOV,MOV,MOV,MOV,MOV) (1 byte) (2 cycles) 1 PC Op Code 1 2 ?? IO ? * This should be accurate. 3 Register, Direct -- A,d; X,d; Y,d (ADC,AND,CMP,CMP,CMP,EOR,MOV,MOV,MOV,OR,SBC) (2 bytes) (3 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO Data 1 * Verified by blargg. 4 Register, Direct Indexed -- A,d+X; X,d+Y; Y,d+X (ADC,AND,CMP,EOR,MOV,MOV,MOV,OR,SBC) (2 bytes) (4 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 ?? IO ? 4 DO Data 1 * blargg verified Data read is cycle 4. * 2 and 3 could be swapped, but that would be odd. 5a Register, Indirect -- A,(X) (ADC,AND,CMP,EOR,MOV,OR,SBC) (1 byte) (3 cycles) 1 PC Op Code 1 2 ?? IO ? 3 X Data 1 * Verified by blargg. 5b Register, Indirect++ -- A,(X)+ (MOV) (1 byte) (4 cycles) 1 PC Op Code 1 2 ?? IO ? 3 X Data 1 4 ?? IO ? * Verified by blargg. 6 Register, Indexed Indirect -- A,[d+X] (ADC,AND,CMP,EOR,MOV,OR,SBC) (2 bytes) (6 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 ?? IO ? 4 DO+X AAL 1 5 DO+X+1 AAH 1 6 AA Data 1 * blargg verifies the Data read is cycle 6. * Cycles 2-5 could be rearranged, but this is most likely. 7 Register, Indirect Indexed -- A,[d]+Y (ADC,AND,CMP,EOR,MOV,OR,SBC) (2 bytes) (6 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO AAL 1 4 DO+1 AAH 1 5 ?? IO ? 6 AA+Y Data 1 * blargg verifies the Data read is cycle 6. * Cycles 2-5 could be rearranged, but this is most likely. 8 Register, Absolute -- A,!a; X,!a; Y,!a (ADC,AND,CMP,CMP,CMP,EOR,MOV,MOV,MOV,OR,SBC) (3 bytes) (4 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH 1 4 AA Data 1 * Verified by blargg. * 2 and 3 could be swapped, but that would be odd. 9 Register, Absolute Indexed -- A,!a+X; A,!a+Y (ADC,ADC,AND,AND,CMP,CMP,EOR,EOR,MOV,MOV,OR,OR,SBC,SBC) (3 bytes) (5 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH 1 4 ?? IO ? 5 AA+X/Y Data 1 * blargg verifies Data read is cycle 5. * Cycles 2-4 could be in other orders, but this is most likely. 10 Direct, Immediate -- d,#i (ADC,AND,CMP,EOR,MOV,OR,SBC) (3 bytes) (5 cycles) 1 PC Op Code 1 2 PC+1 Data 1 1 3 PC+2 DO 1 4 DO Data 2 (read) 1 5 DO Data 2 (write) 0 * Verified by blargg. 2 and 3 could be swapped, but that's unlikely. * Yes, RMW even for MOV. * CMP does not write for cycle 5; does it IO or read again? 11 Direct, Register -- d,A; d,X; d,Y (MOV,MOV,MOV) (2 bytes) (4 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO Data (read) 1 4 DO Data (write) 0 * Verified by blargg. * Yes, RMW even for MOV 12 Direct Indexed, Register -- d+X,A; d+X,Y; d+Y,X (MOV,MOV,MOV) (2 bytes) (5 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 ?? IO 1 4 DO+X/Y Data (read) 1 5 DO+X/Y Data (write) 0 * Verified by blargg. 2 and 3 could be swapped, but that's unlikely. * Yes, RMW even for MOV 13a Indirect, Register -- (X),A (MOV) (1 byte) (4 cycles) 1 PC Op Code 1 2 ?? IO ? 3 X Data (read) 1 4 X Data (write) 0 * Verified by blargg. * Yes, RMW even for MOV 13b Indirect++, Register -- (X)+,A (MOV) (1 byte) (4 cycles) 1 PC Op Code 1 2 ?? IO ? 3 ?? IO ? 4 DO Data (write) 0 * Verified by blargg. * No RMW here 14 Indexed Indirect, Register -- [d+X],A (MOV) (2 bytes) (7 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 ?? IO ? 4 DO+X AAL 1 5 DO+X+1 AAH 1 6 AA Data (read) 1 7 AA Data (write) 0 * blargg verifies cycles 6 and 7. * Yes, RMW even for MOV 15 Indirect Indexed, Register -- [d]+Y,A (MOV) (2 bytes) (7 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO AAL 1 4 DO+1 AAH 1 5 ?? IO ? 6 AA+Y Data (read) 1 7 AA+Y Data (write) 0 * blargg verifies cycles 6 and 7. * Yes, RMW even for MOV 16 Absolute, Register -- !a,A; !a,X; !a,Y (MOV,MOV,MOV) (3 bytes) (5 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH 1 4 AA Data (read) 1 5 AA Data (write) 0 * Verified by blargg. 2 and 3 could be swapped, but that's unlikely. * Yes, RMW even for MOV 17 Absolute Indexed, Register -- !a+X,A; !a+Y,A (MOV,MOV) (3 bytes) (6 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH 1 4 ?? IO ? 5 AA+X/Y Data (read) 1 6 AA+X/Y Data (write) 0 * blargg verified cycles 5 and 6. * Yes, RMW even for MOV 18 Direct, Direct -- dd,ds (ADC,AND,CMP,EOR,MOV,OR,SBC) (3 bytes) (5 or 6 cycles) 1 PC Op Code 1 2 PC+1 DS 1 3 DS Data 1 1 4 PC+2 DD 1 [5] DD Data 2 (read) 1 6 DD Data 2 (write) 0 * Verified by blargg. * Skip cycle 5 for MOV, no RMW. * CMP does not write for cycle 6; does it IO or read again? 19 Indirect, Indirect -- (X),(Y) (ADC,AND,CMP,EOR,OR,SBC) (1 byte) (5 cycles) 1 PC Op Code 1 2 ?? IO ? 3 Y Data 1 1 4 X Data 2 (read) 1 5 X Data 2 (write) 0 * Verified by blargg. * CMP does not write for cycle 5; it is an IO cycle. 20a Direct (RMW) -- d (ASL,CLR1,DEC,INC,LSR,ROL,ROR,SET1) (2 bytes) (4 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO Data (read) 1 4 DO Data (write) 0 * Verified by blargg. 20b Direct (RMW) -- m.b (NOT1) (3 bytes) (5 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH & BIT 1 4 DO Data (read) 1 5 DO Data (write) 0 * Verified by blargg. 2 and 3 could be swapped, but that's unlikely. 21 Direct Indexed (RMW) -- d+X (ASL,DEC,INC,LSR,ROL,ROR) (2 bytes) (5 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 ?? IO ? 4 DO Data (read) 1 5 DO Data (write) 0 * blargg verified cycles 4 and 5. * 2 and 3 could be swapped, but that would be odd. 22 Absolute (RMW) -- !a (ASL,DEC,INC,LSR,ROL,ROR,TCLR1,TSET1) (3 bytes) (5 or 6 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH 1 [4] AA Data (read) 1 5 AA Data (read) 1 6 AA Data (write) 1 * Verified by blargg. * 2 and 3 could be swapped, but that would be odd. * Cycle 4 only for TSET1 and TCLR1. 23 Carry, MemBit -- C,m.b; C,/m.b (AND1,AND1,MOV1,EOR1,OR1,OR1) (3 bytes) (4 or 5 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH & BIT 1 4 AA Data 1 [5] ?? IO ? * Verified by blargg. * Cycle 5 present only in EOR1 and OR1. 24 MemBit, Carry -- m.b,C MOV1 m.b, C CA 3 6 (m.b) = C ........ (MOV1) (3 bytes) (6 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH & BIT 1 4 AA Data (read) 1 5 ?? IO ? 6 AA Data (write) 0 * Verified by blargg. 2 and 3 could be swapped, but that's unlikely. 25 Implied (ASL,CLRC,CLRP,CLRV,DAA,DAS,DEC,DEC,DEC,DI,DIV,EI,INC,INC,INC,LSR,MUL,NOP, NOTC,ROL,ROR,SETC,SETP,XCN) (1 byte) (2, 3, 5, 9, or 12 cycles) 1 PC Op Code 1 2 ?? IO ? [3-12] ?? IO ? * This should be accurate. * The common theme here is that all these do no memory accesses. 26 Word-Register, Direct -- YA,d (ADDW,CMPW,MOVW,SUBW) (2 bytes) (4 or 5 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO Data 1 Low 1 [4] ?? IO ? 5 DO+1 Data 1 High 1 * Verified by blargg. * No cycle 4 for CMPW 27 Direct, Word-Register, Direct -- d,YA (MOVW) (2 bytes) (5 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO Data Low (read) 1 4 DO Data Low 0 5 DO+1 Data High 0 * Verified by blargg. * Yes, RMW on low byte only... 28 Word-Direct (RMW) -- d (DECW,INCW) (2 bytes) (6 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO Data 1 Low 1 4 DO Data 1 Low 0 5 DO+1 Data 1 High 1 6 DO+1 Data 1 High 0 * Verified by blargg. 29 Stack Ops (POP,POP,POP,POP,PUSH,PUSH,PUSH,PUSH) (1 byte) (4 cycles) 1 PC Op Code 1 2 ?? IO ? 3 S Data 0/1 4 ?? IO ? * Or is it Data-IO-IO or IO-IO-Data? 30a JMP Absolute -- !a (JMP) (3 bytes) (3 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH 1 (1) New PC Op Code 1 * This should be accurate. 30b JMP Absolute Indexed Indirect -- [!a+X] (JMP) (3 bytes) (6 cycles) 1 PC Op Code 1 2 PC+1 AAL 1 3 PC+2 AAH 1 4 ?? IO ? 5 AA PCL 1 6 AA+1 PCH 1 (1) New PC Op Code 1 * This should be fairly accurate. * Any penalty for AA+X crossing pages? 31a Branch -- r (BCC,BCS,BEQ,BMI,BNE,BPL,BVC,BVS,BRA) (2 bytes) (2 or 4 cycles) 1 PC Op Code 1 2 PC+1 R 1 [3] ?? IO ? [4] ?? IO ? * This should be accurate. * Cycles 3 and 4 only present if branch is taken. * BRA always takes the branch. 21b Test-and-Branch Direct -- d,r; d.b,r (BBC,BBS,CBNE) (3 bytes) (5 or 7 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO Data 1 4 PC+2 R 1 5 ?? IO ? [6] ?? IO ? [7] ?? IO ? * Cycles 6 and 7 only present if branch is taken * Cycles 1-3 are verified by blargg. 31c Test-and-Branch Direct Indexed -- d+X,r (CBNE) (3 bytes) (6 or 8 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 ?? IO ? 4 DO+X Data 1 5 PC+2 R 1 6 ?? IO ? [7] ?? IO ? [8] ?? IO ? * blargg verifies Data read is cycle 4; the rest is guesswork. * Order of cycles is unknown, except the two extras are probably are at the end. 31d Modify-and-Branch Direct -- d,r; d.b,r (DBNZ) (3 bytes) (5 or 7 cycles) 1 PC Op Code 1 2 PC+1 DO 1 3 DO Data (read) 1 4 DO Data-1 (write) 0 5 PC+2 R 1 [6] ?? IO ? [7] ?? IO ? * blargg verifies cycles 3 and 4. * Cycles 6 and 7 only present if branch is taken * Order of cycles is unknown, except the two extras are probably are at the end. 31e Modify-and-Branch Register -- Y,r (DBNZ) (2 bytes) (4 or 6 cycles) 1 PC Op Code 1 2 PC+1 R 1 3 ?? IO ? 4 ?? IO ? [5] ?? IO ? [6] ?? IO ? * Cycles 5 and 6 only present if branch is taken * Order of cycles is unknown, except the two extras are probably are at the end. 32a CALL (CALL) (3 bytes) (8 cycles) 1 PC Op Code 1 2 SP PCH 0 3 SP-1 PCL 0 4 ?? IO ? 5 PC+1 AAL 1 6 PC+2 AAH 1 7 ?? IO ? 8 ?? IO ? (1) new PC Op Code 1 * WTF with all the IO cycles? * Order of reading new addr and pushing old addr may be wrong. 32b PCALL (PCALL) (2 bytes) (6 cycles) 1 PC Op Code 1 2 SP PCH 0 3 SP-1 PCL 0 4 PC+1 U 1 5 Vec AAL 1 6 Vec+1 AAH 1 (1) new PC Op Code 1 * Order of reading new addr and pushing old addr may be wrong. 32c TCALL (TCALL) (1 byte) (8 cycles) 1 PC Op Code 1 2 SP PCH 0 3 SP-1 PCL 0 4 ?? IO ? 5 Vec AAL 1 6 Vec+1 AAH 1 7 ?? IO ? 8 ?? IO ? (1) new PC Op Code 1 * WTF with all the IO cycles? * Order of reading new addr and pushing old addr may be wrong. 32d BRK (BRK) (1 byte) (8 cycles) 1 PC Op Code 1 2 SP PCH 0 3 SP-1 PCL 0 4 SP-2 PSW 0 5 $FFDE AAL 1 6 $FFDF AAH 1 7 ?? IO ? 8 ?? IO ? (1) new PC Op Code 1 * WTF with all the IO cycles? * Order of reading new addr and pushing old addr may be wrong. 33a RET (RET) (1 byte) (5 cycles) 1 PC Op Code 1 2 SP PCL 0 3 SP+1 PCH 0 4 ?? IO ? 5 ?? IO ? (1) new PC Op Code 1 * WTF with all the IO cycles? 33b RET1 (RET1) (1 byte) (6 cycles) 1 PC Op Code 1 2 SP PSW 0 3 SP+1 PCL 0 4 SP+2 PCH 0 5 ?? IO ? 6 ?? IO ? (1) new PC Op Code 1 * WTF with all the IO cycles?